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參數(shù)資料
| 型號(hào)： | DS1308U-33+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC 56BYTE NVRAM I2C 8UMAX |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 閏年，NVSRAM，方波輸出 |
| 存儲(chǔ)容量： | 56B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 3 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1308
Low-Current I2C RTC with 56-Byte NV RAM
12
Maxim Integrated
External Synchronization
When an external clock reference is used, the input from
SQW/CLKIN is divided down to 1Hz. The 1Hz from the
divider (Ext-1Hz, see Functional Diagram) is used to
correct the 1Hz that is derived from the 32.768kHz oscil-
lator (Osc-1Hz). As Osc-1Hz drifts in relation to Ext-1Hz,
Osc-1Hz is digitally adjusted.
As shown in the Functional Diagram, the three highest
frequencies driving the SQW/CLKIN pin are derived
from the uncorrected oscillator, while the 1Hz output is
derived from the adjusted Osc-1Hz signal.
Conceptually, the circuit can be thought of as two 1Hz
signals, one derived from the internal oscillator and
the other from the external reference clock, with the
oscillator-derived 1Hz signal being locked to the 1Hz
signal derived from the external reference clock. The
edges of the 1Hz signals do not need to be aligned with
each other. While the external clock source is present
and within tolerance, the Ext-1Hz and Osc-1Hz maintain
their existing lock, regardless of their edge alignment,
with periodic correction of the Osc-1Hz signal. If the
external signal is lost and then regained sometime later,
the signals re-lock with whatever new alignment exists
The Ext-1Hz is used by the device as long as it is within
tolerance, which is about 0.8% of Osc-1Hz. While Ext-1Hz
is within tolerance, the skew between the two signals may
shift until a change of about 7.8ms accumulates, after
which Osc-1Hz signal is adjusted (Figure 5). The adjust-
ment is accomplished by digitally adjusting the 32kHz
oscillator divider chain.
Figure 4. Loss and Reacquisition of External Reference Clock
Figure 5. Drift Adjustment of Internal 1Hz to External Reference Clock
OSC-1Hz
FROM OSCILLATOR
EXT-1Hz
FROM EXTERNAL REFERENCE
SKEW
BREAK IN EXTERNAL REFERENCE SIGNAL
CURRENT LOCK
SHIFTED BACK TO CURRENT LOCK
DRIFT AFTER N CYCLES
OSC-1Hz
FROM OSCILLATOR
EXT-1Hz
FROM EXTERNAL REFERENCE
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