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參數(shù)資料
| 型號： | DS1307N |
| 英文描述： | 64 X 8 Serial Real Time Clock |
| 中文描述： | 64 × 8串行實時時鐘 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 165K |
| 代理商： | DS1307N |
DS1307
9 of 11
AC ELECTRICAL CHARACTERISTICS
(0
°
C to 70
°
C or -40
°
C to +85
°
C; V
CC
=4.5V to 5.5V)
SYMBOL
MIN
TYP
f
SCL
0
t
BUF
4.7
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
Capacitive Load for each Bus Line
I/O Capacitance
Crystal Specified Load Capacitance
MAX
100
UNITS
kHz
μ
s
NOTES
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
4.0
4.7
4.0
4.7
μ
s
μ
s
μ
s
μ
s
5
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
C
B
C
I/O
0
μ
s
ns
ns
ns
μ
s
pF
pF
pF
6, 7
250
1000
300
4.7
400
8
10
12.5
NOTES:
1.
All voltages are referenced to ground.
2.
Logic zero voltages are specified at a sink current of 5 mA at V
CC
=4.5V, V
OL
=GND for capacitive
loads.
3.
I
CCS
specified with V
CC
=5.0V and SDA, SCL=5.0V.
4.
V
CC
=0V, V
BAT
=3V.
5.
After this period, the first clock pulse is generated.
6.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
IHMIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
8.
C
B
- total capacitance of one bus line in pF.
9.
I
CCA
- SCL clocking at max frequency = 100 kHz.
10.
SCL only.
11.
SDA and SQW/OUT
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