參數(shù)資料
型號: DS1307
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDIP8
封裝: 0.300 INCH, PLASTIC, DIP-8
文件頁數(shù): 8/14頁
文件大?。?/td> 361K
代理商: DS1307
DS1307 64 x 8, Serial, I2C Real-Time Clock
3 of 14
AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
0
100
kHz
Bus Free Time Between a STOP and
START Condition
tBUF
4.7
s
Hold Time (Repeated) START
Condition
tHD:STA
(Note 4)
4.0
s
LOW Period of SCL Clock
tLOW
4.7
s
HIGH Period of SCL Clock
tHIGH
4.0
s
Setup Time for a Repeated START
Condition
tSU:STA
4.7
s
Data Hold Time
tHD:DAT
0
s
Data Setup Time
tSU:DAT
(Notes 5, 6)
250
ns
Rise Time of Both SDA and SCL
Signals
tR
1000
ns
Fall Time of Both SDA and SCL
Signals
tF
300
ns
Setup Time for STOP Condition
tSU:STO
4.7
s
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pin Capacitance (SDA, SCL)
CI/O
10
pF
Capacitance Load for Each Bus
Line
CB
(Note 7)
400
pF
Note 1:
All voltages are referenced to ground.
Note 2:
Limits at -40°C are guaranteed by design and are not production tested.
Note 3:
ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V.
Note 4:
After this period, the first clock pulse is generated.
Note 5:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 6:
The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 7:
CB—total capacitance of one bus line in pF.
相關(guān)PDF資料
PDF描述
DS1315EN-5 0 TIMER(S), REAL TIME CLOCK, PDSO20
DS1315-5 0 TIMER(S), REAL TIME CLOCK, PDIP16
DS1315EN-33 0 TIMER(S), REAL TIME CLOCK, PDSO20
DS1315N-5 0 TIMER(S), REAL TIME CLOCK, PDIP16
DS1315E-33 0 TIMER(S), REAL TIME CLOCK, PDSO20
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參數(shù)描述
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