
DS1305
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INTCN (Interrupt Control) - This bit controls the relationship between the two time of day alarms and
the interrupt output pins. When the INTCN bit is set to a logic 1, a match between the timekeeping
registers and the Alarm 0 registers will activate the INT0 pin (provided that the alarm is enabled) and a
match between the timekeeping registers and the Alarm 1 registers will activate the INT1 pin (provided
that the alarm is enabled). When the INTCN bit is set to a logic 0, a match between the timekeeping
registers and either Alarm 0 or Alarm 1 will activate the INT0 pin (provided that the alarms are enabled).
INT1
has no function when INTCN is set to a logic 0.
AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0 . When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1 (when INTCN=1) or to assert INT0 (when INTCN=0).
When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal.
STATUS REGISTER (READ 10H)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
00000
IRQF1
IRQF0
IRQF0 (Interrupt 0 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin will go low.
IRQF0 is cleared when any of the Alarm 0 registers are read or written.
IRQF1 (Interrupt 1 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 1 registers. This flag can be used to generate an interrupt on either INT0 or
INT1
depending on the status of the INTCN bit in the Control Register. If the INTCN bit is set to a logic
1 and IRQF1 is at a logic 1 (and AIE1 bit is also a logic 1), the INT1 pin will go low. If the INTCN bit is
set to a logic 0 and IRQF1 is at a logic 1 (and AIE1 bit is also a logic 1), the INT0 pin will go low.
IRQF1 is cleared when any of the Alarm 1 registers are read or written.
TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
This register controls the trickle charge characteristics of the DS1305. The simplified schematic of
Figure 3 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits
4-7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of
1010 will enable the trickle charger. All other patterns will disable the trickle charger. The DS1305
powers up with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether one
diode or two diodes are connected between VCC1 and VCC2. If DS is 01, one diode is selected. If DS is
10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independent of TCS. The
RS bits select the resistor that is connected between VCC1 and VCC2. The resistor is selected by the resister
select (RS) bits as shown in Table 2.