- 您現(xiàn)在的位置：買賣IC網 > PDF目錄97858 > DS1248Y-70 (DALLAS SEMICONDUCTOR) 0 TIMER(S), REAL TIME CLOCK, DMA32 PDF資料下載
參數(shù)資料
| 型號： | DS1248Y-70 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, DMA32 |
| 封裝： | MODULE, DIP-32 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 279K |
| 代理商： | DS1248Y-70 |
DS1248/DS1248P
4 of 21
DATA RETENTION MODE
The 5 volt device is fully accessible and data can be written or read only when VCC is greater than VPF .
However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3 volt device is fully accessible and data can be written or read only when VCC is greater than VPF .
When VCC fall as below the power fail point, VPF , access to the device is inhibited. If VPF is less than VBAT ,
the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF . If VPF is
greater than VBAT , the device power is switched from VCC to the backup supply (VBAT ) when VCC drops
below VBAT . RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of
64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable ( CE ), Output Enable ( OE ), and Write Enable ( WE ).
Initially, a read cycle to any
memory location using the CE and OE control of the Phantom Clock starts the pattern recognition
sequence by moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive
write cycles are executed using the CE and WE control of the SmartWatch. These 64 write cycles are
used only to gain access to the Phantom Clock. Therefore, any address to the memory in the socket is
acceptable. However, the write cycles generated to gain access to the Phantom Clock are also writing
data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just
one address location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it
is compared to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the
next location of the comparison register and awaits the next write cycle. If a match is not found, the
pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time
during pattern recognition, the present sequence is aborted and the comparison register pointer is reset.
Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the
comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for
64–bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed.
The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on
the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be
interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer
sequence to the Phantom Clock.
相關PDF資料 |
PDF描述 |
|---|---|
| DS1248YP-70 | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| DS1248W-120 | REAL TIME CLOCK, PDIP32 |
| DS1248WP-120 | REAL TIME CLOCK, DMA34 |
| DS1250ABP-70 | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
| DS1250AB-100 | 512K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DIP32 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1248Y-70+ | 功能描述:實時時鐘 1024k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1248Y70IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:1024k NV SRAM with Phantom Clock |
| DS1248Y-70IND | 功能描述:IC NVSRAM 1MBIT 70NS 32DIP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN EP 包裝:管件 |
| DS1248Y-70IND+ | 功能描述:實時時鐘 1024k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1248YP/WP | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:PowerCap with Crystal |
發(fā)布緊急采購，3分鐘左右您將得到回復。