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參數(shù)資料
| 型號： | DS1244WP-120 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| 封裝： | POWERCAP MODULE BOARD-34 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 273K |
| 代理商： | DS1244WP-120 |
DS1244/DS1244P
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RAM WRITE MODE
The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The 5 volt device is fully accessible and data can be written or read only when VCC is greater than VPF .
However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3 volt device is fully accessible and data can be written or read only when VCC is greater than VPF .
When VCC fall as below the power fail point, VPF , access to the device is inhibited. If VPF is less than VBAT ,
the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF . If VPF is
greater than VBAT , the device power is switched from VCC to the backup supply (VBAT ) when VCC drops
below VBAT . RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels.
All control, data, and address signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable ( CE ), Output Enable ( OE ), and Write Enable ( WE ). Initially, a read cycle to any memory
location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by
moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the Phantom Clock.
Therefore, any address to the memory in the socket is acceptable.
However, the write cycles generated to gain access to the Phantom Clock are also writing data to a
location in the mated RAM. The preferred way to manage this requirement is to set aside just one address
location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared
to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location
of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not
advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern
recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64–bits, the
Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1244Y-70 | 0 TIMER(S), REAL TIME CLOCK, PDMA28 |
| DS1244Y | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| DS1245AB-100 | 128K X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA32 |
| DS1245Y-120 | 128K X 8 NON-VOLATILE SRAM MODULE, 120 ns, DMA32 |
| DS1245AB-85 | 128K X 8 NON-VOLATILE SRAM MODULE, 85 ns, DMA32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1244WP-120+ | 功能描述:實(shí)時時鐘 256k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1244WP-120IND | 功能描述:IC NVSRAM 256KBIT 120NS 34PCM RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 實(shí)時時鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| DS1244WP-120IND+ | 功能描述:實(shí)時時鐘 256k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1244Y | 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:Real Time Clock, Non-Volatile, 28 Pin, Plastic, DIP |
| DS1244Y120 | 制造商:Maxim Integrated Products 功能描述: |
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