- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9402 > DS1243Y-120+ (Maxim Integrated Products)IC NVSRAM 64KBIT 120NS 28DIP PDF資料下載
參數(shù)資料
| 型號： | DS1243Y-120+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 64KBIT 120NS 28DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 類型： | Phantom 計(jì)時(shí)芯片 |
| 特點(diǎn)： | 閏年 |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP 模塊（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-EDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1432 (CN2011-ZH PDF) |
DS1243Y
4 of 14
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable ( CE ), Output Enable ( OE ), and Write Enable ( WE ). Initially, a read cycle to any memory
location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by
moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable. However,
the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the
mated RAM. The preferred way to manage this requirement is to set aside just one address location in
RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of
the 64–bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the Phantom Clock is
enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause
the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the
WE
pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without
interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.
PHANTOM CLOCK REGISTER INFORMATION
The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3904U-020+ | IC POT NV TRIPLE 128POS 8-USOP |
| DS1804Z-010+T&R | IC POT TRIMMER NV 10KOHM 8SOIC |
| DS1554P-70+ | IC RTC RAM Y2K 5V 70NS 34-PCM |
| MAX5434NEZT+T | IC POT DGTL 32TAP NV TSOT23-6 |
| DS1554WP-120+ | IC RTC RAM Y2K 3.3V 120NS 34-PCM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1243Y120+ | 制造商:Maxim Integrated Products 功能描述: |
| DS1243Y-120+ | 功能描述:實(shí)時(shí)時(shí)鐘 64k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1243Y-120+ | 制造商:Maxim Integrated Products 功能描述:IC |
| DS1243Y-150 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:64K NV SRAM with Phantom Clock |
| DS1243Y4120 | 制造商:Maxim Integrated Products 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。