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參數(shù)資料
| 型號： | DS1243Y-120+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC NVSRAM 64KBIT 120NS 28DIP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 12 |
| 類型： | Phantom 計時芯片 |
| 特點： | 閏年 |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP 模塊（0.600"，15.24mm） |
| 供應商設備封裝： | 28-EDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1432 (CN2011-ZH PDF) |
DS1243Y
13 of 14
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 50pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write
Cycle 1, the output buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator
running.
10. tWR is a function of the latter occurring edge of WE or CE .
11. tDH and tDS are a function of the first occurring edge of WE or CE .
12. RST (Pin1) has an internal pullup resistor.
13. Real-Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
28 EDIP
MDT28+1
—
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1243Y120+ | 制造商:Maxim Integrated Products 功能描述: |
| DS1243Y-120+ | 功能描述:實時時鐘 64k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1243Y-120+ | 制造商:Maxim Integrated Products 功能描述:IC |
| DS1243Y-150 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:64K NV SRAM with Phantom Clock |
| DS1243Y4120 | 制造商:Maxim Integrated Products 功能描述: |
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