參數(shù)資料
型號: DS1020-50
英文描述: Programmable 8-Bit Silicon Delay Line
中文描述: 可編程8位硅延遲線
文件頁數(shù): 5/9頁
文件大?。?/td> 193K
代理商: DS1020-50
DS1021
5 of 9
DALLAS SEMICONDUCTOR TEST CIRCUIT
Figure 4
TEST SETUP DESCRIPTION
Figure 4 illustrates the hardware configuration used for measuring the timing parameters of the DS1021.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1021 serial and
parallel ports are controlled by interfaces to a central computer. All measurements are fully automated
with each instrument controlled by the computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
25°C ± 3°C
5.0V ± 0.1V
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
50 ohms max.
3.0 ns max.
(measured between 0.6V and 2.4V)
500 ns (DS1021–25)
2 μs (DS1021–50)
1 μs (DS1021–25)
4 μs (DS1021–50)
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
NOTE: Above conditions are for test only and do not restrict the operation of the device under other data
sheet conditions.
OUTPUT:
Output is loaded with a 74F04. Delay is measured between the 1.5V level of the rising edge of the input
signal and the 1.5V level of the corresponding edge of the output.
DS1021
相關(guān)PDF資料
PDF描述
DS1021-25 ENDPLATE FOR SRU4/SR4-T15/SRM4
DS1021-50 Programmable 8-Bit Silicon Delay Line
DS1023-025 8-Bit Programmable Timing Element
DS1023-050 8-Bit Programmable Timing Element
DS1023-100 8-Bit Programmable Timing Element
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