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參數(shù)資料
| 型號(hào)： | DPS512X32MFY3-35B |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, QMA68 |
| 封裝： | LEADLESS, STACK, SLCC-68 |
| 文件頁(yè)數(shù)： | 8/8頁(yè) |
| 文件大小： | 811K |
| 代理商： | DPS512X32MFY3-35B |
DPS512X32MFn3
Dense-Pac Microsystems, Inc.
ORDERING INFORMATION
Dense-Pac Microsystems, Inc.
7321 Lincoln Way Garden Grove , California 92841-1431
(714) 898-0007 (800) 642-4477 (Outside CA) FAX: (714) 897-1772 http://www.dense-pac.com
WAVEFORM KEY
Data Valid
Transition from
Data Undefined
HIGH to LOW
LOW to HIGH
or Don’t Care
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level).
3. Stresses greater than those under
ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of
±500mV from steady state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase
to the outputs must not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
30A154-04
REV. B
8
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