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參數(shù)資料
| 型號： | DP8440V |
| 英文描述： | DRAM Controller |
| 中文描述： | DRAM控制器 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 644K |
| 代理商： | DP8440V |
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6.0 Refresh Modes
The DP8440/41 support auto-internal refresh, and external-
ly control refresh. The DP8440/41 arbitrates between re-
freshes and accesses and guarantees precharge timings af-
ter every access and refresh. The DRAM controller will nev-
er interrupt an access in progress to do a refresh, nor will it
interrupt a refresh in progress when an access is requested.
After every refresh the DRAM controller will guarantee the
programmed precharge time before RAS can assert for a
new access or for a second refresh. The refresh period can
be programmed for 15
m
s or for 120
m
s.
6.1 AUTO-INTERNAL REFRESH
This refresh scheme is completely transparent to the CPU.
The DP8440/41 will refresh the DRAM every 15
m
s or
120
m
s, depending on the programming selection. When the
refresh counter expires (every 15
m
s or 120
m
s) the RFRQ
output asserts. On the next rising edge of clock RFIP as-
serts and, one clock period later, RASs assert. RFIP ne-
gates on the same clock edge that RASs negate. If the user
is doing long page or burst accesses, the DP8440/41 will
keep track of up to 6 missed refreshes. At the end of the
access the DRAM controller will burst refresh the locations
missed during the access.
TL/F/11718–10
FIGURE 14. Autointernal Refresh (2T of RAS Low and Precharge)
20
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP8440V-40 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver |
| DP8440VLJ-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DP8440VLJ-40 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver |
| DP8441 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DP84412J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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