參數(shù)資料
型號: DP83848YBX/NOPB
廠商: National Semiconductor
文件頁數(shù): 81/86頁
文件大?。?/td> 0K
描述: IC TXRX ETHERNET PHYTERA 48-LQFP
產(chǎn)品培訓(xùn)模塊: PHYTER® Family
標準包裝: 1,000
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: 以太網(wǎng)
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-LQFP 裸露焊盤(7x7)
包裝: 帶卷 (TR)
其它名稱: DP83848YBX
81
www.national.com
DP
83
84
8
Y
B
8.2.27 RMII Receive Timing
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may
toggle synchronously at the end of the packet to indicate CRS deassertion.
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of
receive data.
Parameter
Description
Notes
Min
Typ
Max
Units
T2.27.1
X1 Clock Period
50 MHz Reference Clock
20
ns
T2.27.2
RXD[1:0], CRS_DV, RX_DV
and RX_ER output delay from
X1 rising
2
14
ns
T2.27.3
CRS ON delay
From JK symbol on PMD Receive Pair to
initial assertion of CRS_DV
18.5
bits
T2.27.4
CRS OFF delay
From TR symbol on PMD Receive Pair to
initial deassertion of CRS_DV
27
bits
T2.27.5
RXD[1:0] and RX_ER latency
From symbol on Receive Pair. Elasticity
buffer set to default value (01)
38
bits
CRS_DV
X1
RXD[1:0]
RX_ER
PMD Input Pair
IDLE
Data
(J/K)
Data
(TR)
RX_DV
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