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參數(shù)資料
| 型號(hào)： | DP83848YBX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 11/86頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX ETHERNET PHYTERA 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | PHYTER® Family |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | DP83848YBX |
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18
D
P
838
48
YB
2.3 PHY Address
The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.
The DP83848YB can be set to respond to any of 32 possi-
ble PHY addresses via strap pins. The information is
latched into the PHYCR register (address 19h, bits [4:0]) at
device power-up and hardware reset. The PHY Address
pins are shared with the RXD and COL pins. Each
DP83848YB or port sharing an MDIO bus in a system must
have a unique physical address.
The DP83848YB supports PHY Address strapping values
0 (<00000>) through 31 (<11111>). Strapping PHY
Address 0 puts the part into Isolate Mode. It should also
be noted that selecting PHY Address 0 via an MDIO write
to PHYCR will not put the device in Isolate Mode. See
Section 2.3.1for more information.
For further detail relating to the latch-in timing requirements
of the PHY Address pins, as well as the other hardware
configuration pins, refer to the Reset summary in
Since the PHYAD[0] pin has weak internal pull-up resistor
and PHYAD[4:1] pins have weak internal pull-down resis-
tors, the default setting for the PHY address is 00001
(01h).
Refer to Figure 2 for an example of a PHYAD connection to
external components. In this example, the PHYAD strap-
ping results in address 00011 (03h).
2.3.1 MII Isolate Mode
The DP83848YB can be put into MII Isolate mode by writ-
ing to bit 10 of the BMCR register or by strapping in Physi-
cal Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.
When in the MII isolate mode, the DP83848YB does not
respond to packet data present at TXD[3:0], TX_EN inputs
and presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848YB will continue to respond
to all management transactions.
While in Isolate mode, the PMD output pair will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
The DP83848YB can Auto-Negotiate or parallel detect to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848YB is in Isolate mode.
Table 2. PHY Address Mapping
Pin #
PHYAD Function
RXD Function
42
PHYAD0
COL
43
PHYAD1
RXD_0
44
PHYAD2
RXD_1
45
PHYAD3
RXD_2
46
PHYAD4
RXD_3
Figure 2. PHYAD Strapping Example
CO
L
RXD_
0
RXD_
1
RXD_
2
RXD_
3
VCC
2.2
k
PHYAD0 = 1
PHYAD1 = 1
PHYAD2 = 0
PHYAD3 = 0
PHYAD4= 0
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