參數(shù)資料
型號(hào)： DP83848CVVX/NOPB
廠商： National Semiconductor
文件頁(yè)數(shù)： 30/86頁(yè)
文件大?。?/td> 0K
描述： TXRX ETHERNET PHYTER 48LQFP
產(chǎn)品培訓(xùn)模塊： PHYTER® Family
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： DP83848CVVX/NOPBDKR
35
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DP
83
84
8
C
5.4 Power Feedback Circuit
To ensure correct operation for the DP83848C, parallel
caps with values of 10
F (Tantalum) and 0.1 F should be
placed close to pin 23 (PFBOUT) of the device.
Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected
to pin 23 (PFBOUT), each pin requires a small capacitor
(.1
F). See Figure 13 below for proper connections.
5.5 Power Down/Interrupt
The Power Down and Interrupt functions are multiplexed
on pin 7 of the device. By default, this pin functions as a
power down input and the interrupt function is disabled.
Setting bit 0 (INT_OE) of MICR (0x11h) will configure the
pin as an active low interrupt output.
5.5.1 Power Down Control Mode
The PWR_DOWN/INT pin can be asserted low to put the
device in a Power Down mode. This is equivalent to setting
bit 11 (Power Down) in the Basic Mode Control Register,
BMCR (0x00h). An external control signal can be used to
drive the pin low, overcoming the weak internal pull-up
resistor. Alternatively, the device can be configured to ini-
tialize into a Power Down state by use of an external pull-
down resistor on the PWR_DOWN/INT pin. Since the
device will still respond to management register accesses,
setting the INT_OE bit in the MICR register will disable the
PWR_DOWN/INT input, allowing the device to exit the
Power Down state.
Table 8. 50 MHz Oscillator Specification
Parameter
Min
Typ
Max
Units
Condition
Frequency
50
MHz
Frequency
Tolerance
+50
ppm
Operational
Temperature
Frequency
Stability
+50
ppm
Operational
Temperature
Rise / Fall Time
6
nsec
20% - 80%
Jitter
8001
psec
Short term
Jitter
8001
psec
Long term
Symmetry
40%
60%
Duty Cycle
1 This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
Table 9. 25 MHz Crystal Specification
Parameter
Min
Typ
Max
Units
Condition
Frequency
25
MHz
Frequency
Tolerance
+50
ppm
Operational Tem-
perature
Frequency
Stability
+50
ppm
1 year aging
Load Capacitance
25
40
pF
.1
F
10
F
Pin 23 (PFBOUT)
.1
F
.1
F
Pin 18 (PFBIN1)
Pin 37 (PFBIN2)
+
-
Figure 13. Power Feeback Connection
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