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參數(shù)資料
| 型號： | DMA2286 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | DMA 2275, DMA 2286 C/D/D2-MAC Descrambler |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 34/48頁 |
| 文件大?。?/td> | 217K |
| 代理商： | DMA2286 |
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DMA 2275, DMA 2286
34
9.3. Pin Configuration
Fig. 9–2:
DMA 2286 in 68–pin PLCC package
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
29 30 31 32 33 34 35 36 37 38 39
27 28
6
5
4
3
2
1
44
43
42
41
40
68 67 66 65 64 63 62 61
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SDIO
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
IMC
IMI
IMD
RES
BSYNC
MCLK
BDAT
VBIDAT
CPDAT
PDAT
DPDAT
BO0
BO1
BO2
BO3
BO4
BO5
BO6
BO7
GND
GND
GND
GND
GND
VSUP
BI7
BI6
BI5
BI4
BI3
BI2
BI1
BI0
IMBUS
GND
ADIO
ACAS
AA0
AA1
AA2
AA3
AA4
AA5
ARAS
AA6
AA7
GND
SBD
SBI
SR/W
SRAS
ACLK
VSUP
GND
SCAS
AR/W
DMA 2286
9.4. Pin Descriptions
Pin 1 – Sound RAM Data Input/Output (Fig. 9–8)
Pin 1 serves as output for writing sound data into the ex-
ternal sound RAM and as input for reading sound data
from that RAM.
Pins 2 to 6 and 9 to 11 – Sound RAM Address A0 to A7
Output (Fig. 9–11)
These pins are used for addressing the external sound
RAM.
Pin 7 – Sound RAM Read/Write Output (Fig. 9–11)
By means of this output the external sound RAM is
switched to the read or write mode as required.
Pin 8 – Sound RAM Row Address Select Output (Fig.
9–11)
This pin supplies the Row Address Select signal (RAS)
to the external sound RAM.
Pins 12, 13 and 14 – IM Bus Connection (Figs. 9–3 and
9–7)
These pins connect the DMA 2275/2286 to the IM bus.
Via the IM bus the DMA 2275/2286 communicates with
the CCU Central Control Unit.
Pin 15 – Reset Input (Fig. 9–6)
Pin 15 is used for hardware reset. Reset is actuated at
Low level, and at High level the DAM 2275/2286 is ready
for operation.
Pin 16 –
Φ
M Main Clock Input (Fig. 9–5)
By means of this input, the DMA 2275/2286 receives the
required main clock signal of 20.25 MHz form the MCU
2600 Clock Generator IC.
Pin 17 – Burst Sync Input (Fig. 9–3)
By means of this input, the DMA 2275/2286 receives the
required burst sync pulse from the DMA 2271/2281. This
sync pulse is used both as line sync and frame sync.
Pin 19 – Burst Data Input (Fig. 9–3)
By means of this input, the DMA 2275/2286 receives the
decoded burst data of each line from the DMA
2271/2281.
Pin 20 – VBI Data Output (Fig. 9–11)
This pin supplies the descrambled burst data of each
line. This signal may serve as an input signal for the TPU
2735 Teletext Processor.
Pin 21 – Corrected Packet Data Output (Fig. 9–11)
This pin supplies descrambled and error corrected pack-
ets from two subframes required by external teletext or
other data processors.
Pin 22 – Packet Data Input (Fig. 9–3)
Via this pin, the DMA 2275/2286 receives packets of
one subframe from pin 55 of the DMA 2271/2281. These
packets are already de–interleaved, with golay–cor-
rected header and error–corrected PT byte.
Pin 23 – Descrambled Packet Data Output (Fig. 9–11)
This pin supplies descrambled sound packets from one
subframe to pin 56 of the DMA 2271/2281.
Pins 24 to 31 – Baseband B0 to B7 Output (Fig. 9–11)
Via these pins, the DMA 2275/2286 delivers the digital
baseband signal including the descrambled video signal
to the DMA 2271/2281, where it is decoded into luma,
chroma and sound signals.
Pins 32 to 26 and 48, 61 and 62 – Ground
These pins must be connected to the negative (ground)
of the supply voltage.
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