參數(shù)資料
型號： DM93L34
文件頁數(shù)： 135/158頁
文件大?。?/td> 2668K
代理商： DM93L34
Functional Description
The 93L24 5-bit comparators use combinational circuitry to
directly generate “A greater than B” and “A less than B” out-
puts. As evident from the logic diagram, these ouptuts are
generated in only three gate delays. The “A equals B” output
is generated in one additional gate delay by decoding the “A
neither less than nor greater than B” condition with a NOR
gate. All three outputs are activated by the active LOW En-
able Input (E).
Logic Diagram
Tying the A
>
B output from one device into an A input on an-
other device and the A
<
B output into the corresponding B
input permits easy expansion.
The A4 and B4 inputs are the most significant inputs and A0,
B0 the least significant. Thus if A4 is HIGH and B4 is LOW,
the A
>
B output will be HIGH regardless of all other inputs
except E.
DS010199-3
3
www.fairchildsemi.com
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