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| 型號： | DM9000AE |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ethernet Controller with General Processor Interface |
| 中文描述： | 以太網(wǎng)控制器與通用處理器接口 |
| 文件頁數(shù)： | 23/56頁 |
| 文件大小： | 1744K |
| 代理商： | DM9000AE |
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DM9000A
Ethernet Controller with General Processor Interface
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
23
6.31 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9000A starts to pre-fetch the SRAM data
to internal data buffers.
6.32 Memory Data Read Command without Address Increment Register (F1H)
Bit
Name
Default
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
6.33 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1or 2 depends on the operator mode (8-bit or16-bit respectively)
6.34 Memory Data Read_address Register (F4H~F5H)
Bit
Name
Default
7:0
MDRAH
PHS0,RW Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0
MDRAL
PHS0,RW Memory Data Read_ address Low Byte
6.35 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
6.36 Memory data write command with address increment Register (F8H)
Bit
Name
Default
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1 or 2, depends on
the operator mode. (8-bit or 16-bit respectively)
6.37 Memory data write_address Register (FAH~FBH)
Bit
Name
Default
7:0
MDRAH
PHS0,RW Memory Data Write_ address High Byte
7:0
MDRAL
PHS0,RW Memory Data Write_ address Low Byte
6.38 TX Packet Length Register (FCH~FDH)
Bit
Name
Default
7:0
TXPLH
X,R/W
TX Packet Length High byte
7:0
TXPLL
X,,R/W
TX Packet Length Low byte
Description
7:0
MRCMDX
X,RO
Description
7:0
MRCMDX1
X,RO
Description
7:0
MRCMD
X,RO
Description
Description
7:0
MWCMDX
X,WO
Description
7:0
MWCMD
X,WO
Description
Description
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|---|---|
| DM9000AEP | Ethernet Controller with General Processor Interface |
| DM9000 | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| DM9000E | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| DM9006CJ | Gate Expander |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000AEP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:網(wǎng)絡(luò)接口電路 |
| DM9000B | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface |
| DM9000B_12 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface |
| DM9000BE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9000BEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 48LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 48LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 48LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:48; Interface Type:MII; Operating Temperature Min:0C; ;RoHS Compliant: Yes |
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