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參數(shù)資料
| 型號(hào)： | DJIXFLED0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 123/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXFLED0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
125
4.4
Operating Requirements
4.4.1
Power Requirements
The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and
VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). These
inputs may be supplied from a single source although decoupling is required to each respective
ground. The fiber VCCPECL supply can be connected to either 2.5 V or 3.3 V.
A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The
power supply may be either +2.5 V or +3.3 V. VCCIO should be supplied from the same power
source used to supply the controller on the other side of the interface. Refer to
Table 53, “Intel
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%)” on
page 174, Table 54, “Intel LXT9785/LXT9785E Digital I/O DC Electrical Characteristics
(VCCIO = 3.3 V +/- 5%)” on page 175,
and
Table 55, “Intel LXT9785/LXT9785E Digital I/O
DC Electrical Characteristics – SD Pins” on page 175
for I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible. Typical filtering and
decoupling are shown in
Figure 34 on page 168
. The power supplies should be brought up as close
to the same time as possible. However, there are no specific timing requirements.
4.4.2
Clock/SYNC Requirements
4.4.2.1
Reference Clock
The LXT9785/LXT9785E requires a constant enabled reference clock (REFCLK). REFCLK’s
frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used
to generate transmit signals and recover receive signals. A crystal-based clock is recommended
over a derived clock (that is, PLL-based) to minimize transmit jitter. Refer to
Table 56, “Intel
LXT9785/LXT9785E Required Clock Characteristics” on page 175
for clock timing requirements.
For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must always
be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1 are not tied
together.
4.4.2.2
TxCLK Signal (SS-SMII only)
The LXT9785/LXT9785E requires a 125 MHz input transmit clock synchronous with TxData
n
and frequency locked to REFCLK
.
See
Figure 22 on page 141.
4.4.2.3
TxSYNC Signal (SMII/SS-SMII)
The LXT9785/LXT9785E requires a 12.5 MHz input pulse for SMII synchronization. See
Figure 22 on page 141.
4.4.2.4
RxSYNC Signal (SS-SMII only)
The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the RxData
n
outputs. See
Figure 23 on page 141.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXFLED0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFPAD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFPAD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFPAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXFLED0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFPAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFPAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFPAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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