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| 型號(hào)： | DJIXFLCD0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 209/226頁(yè) |
| 文件大小： | 1575K |
| 代理商： | DJIXFLCD0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
211
Table 94. Interrupt Enable Register (Address 18, Hex 12)
Bit
Name
Description
Type
1
Default
15:14
2
RxFIFO Initial
Fill
00 =Reserved
01 =Low, 16 bits
10 =Normal, 32 bits (default)
11 = Jumbo packets, 128 bits
R/W
LSHR
4,5
13
SFD Frame
Alignment
(RxDV asserts
with CRS when
enabled)
10 Mbps
When Register bit 16.5 = 1, preamble is
not suppressed.
R/W
0
0 = Disabled
1 = Enabled
When Register bit 16.5 = 0, SFD is always
aligned, and preamble is suppressed.
100 Mbps
0 = Disabled
1 = Enabled
R/W
0
When enabled, all but one byte of
preamble is suppressed.
12:9
Reserved
Write as 0, ignore on Read
R/W
0000
8
CNTRMSK
Mask for Counter Full
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
7
ANMSK
Mask for Auto-Negotiate Complete
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
6
SPEEDMSK
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
5
DUPLEXMSK
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
4
LINKMSK
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
3
ISOLMSK
Mask for Isolate Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
R/W
0
2
Reserved
Write as 0, ignore on Read
R/W
0
1
INTEN
0 = Disable interrupts on this port
1 = Enable interrupts on this port
R/W
0
0
TINT
0 = Normal operation
1 = Test force interrupt on MDINT
R/W
0
1. R/W = Read/Write
2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = “11” and in
RMII mode, Registers bits 18.15:14 = “11” or “10” cannot be used because the minimum Inter Gap Packet
becomes less than specified in the *IEEE 802.3 specification.
3. SFD Frame Alignment is applicable to SMII and SS-SMII only.
4.
LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset
5. Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see
Table 17, “Intel
LXT9785/LXT9785E Receive FIFO Depth Considerations” on page 50
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXFLCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXFLCD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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