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| 型號(hào)： | DJIXFLCD0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 107/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXFLCD0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
109
3.6
BGA15 Signal Descriptions
3.6.1
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the
two designations. Signal naming conventions are as follows:
Port Number Only.
Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit
Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
Serial Number Only.
A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set
of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
Port and Serial Number.
In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an
underscore, and the serial designation. For example, a set of three Port Configuration signals
would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and
RxData2_0 and RxData2_1.
3.6.2
Signal Descriptions – SMII and SS-SMII Configurations
Table 39
provides the BGA15 signal descriptions.
Table 39. Intel
LXT9785 BGA15 Signal Descriptions (Sheet 1 of 7)
BGA15 Ball
Designation
Symbol
Type
Signal Description
SMII/SS-SMII Common Signal Descriptions
N4,
N2,
K3,
J1,
G3,
E2,
D3,
A5
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
I, ID
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/9785E clocks the data in
synchronously to REFCLK.
C3
L4
REFCLK1
REFCLK0
I
Reference Clock.
The LXT9785/9785E always requires a 125 MHz reference
clock input. Refer to
Section 4.4.2, “Clock/SYNC
Requirements” on page 125
for detailed clock
requirements.
SMII Specific Signal Descriptions
K1
SYNC
I, ID
SMII Synchronization.
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXFLCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXFLCD0SE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0QE001 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLED0SE000 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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