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參數(shù)資料
| 型號： | DG221DY-T1 |
| 廠商： | VISHAY SILICONIX |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 65K |
| 代理商： | DG221DY-T1 |
DG221
4
Siliconix
S-52881—Rev. C, 28-Apr-97
Test Circuits
V–
Figure 2.
Switching Time
t
r
< 10 ns
t
f
< 10 ns
50%
0 V
3 V
t
OFF
t
ON
V
O
V
S
90%
Logic
Input
Switch
Input
Switch
Output
C
L
(includes fixture and stray capacitance)
V+
IN
R
L
R
L
+ r
DS(on)
V
O
= V
S
S
D
–15 V
V
O
GND
2 V
WR
C
L
35 pF
R
L
1 k
+15 V
Figure 3.
WR Switching Time
C
L
(includes fixture and stray capacitance)
V+
IN
R
L
R
L
+ r
DS(on)
V
O
= V
S
S
D
–15 V
V
O
GND
2 V
WR
C
L
35 pF
V–
R
L
1 k
+15 V
0 V
t
r
< 10 ns
t
f
< 10 ns
0 V
3 V
t
OFF
, WR
t
ON
, WR
V
O
V
S
90%
50%
0 V
3 V
WR
IN
V
OUT
Figure 4.
WR Setup Conditions
t
H
= Hold Time
t
S
= Setup Time
t
W
= WR Pulse Width
The latches are level sensitive. When WR is held low the latches are transparent and the switches
respond to the digital inputs. The digital inputs are latched on the rising edge of WR.
t
S
t
S
t
H
t
H
t
W
3 V
3 V
VOUT
WR
IN
50%
50%
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