參數(shù)資料
型號(hào)： DC934A
廠商： Linear Technology
文件頁(yè)數(shù)： 16/20頁(yè)
文件大小： 0K
描述： BOARD DAC LTC2607
軟件下載： QuikEval System
設(shè)計(jì)資源： DC934A Design File
DC934A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
DAC 的數(shù)量： 2
位數(shù)： 16
數(shù)據(jù)接口： I²C
設(shè)置時(shí)間： 10µs
DAC 型： 電壓
工作溫度： 0°C ~ 70°C
已供物品： 板
已用 IC / 零件： LTC2607
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LTC2607/LTC2617/LTC2627
26071727fa
electrical characteristics
timing characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL and LDAC at 0V or VCC, CA0, CA1 and CA2 Floating.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with
the measured DAC at mid-scale, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
l
0
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
s
tLOW
Low Period of the SCL Clock Pin
l
1.3
s
tHIGH
High Period of the SCL Clock Pin
l
0.6
s
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
s
tHD(DAT)
Data Hold Time
l
0
0.9
s
tSU(DAT)
Data Set-Up Time
l
100
ns
tr
Rise Time of Both SDA and SCL Signals
(Note 9)
l
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 9)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
s
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
s
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
l
400
ns
t2
LDAC Low Pulse Width
l
20
ns
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,
VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
UNITS
MIN
TYP MAX MIN
TYP MAX
AC Performance
tS
Settling Time (Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
9
7
9
10
s
Settling Time for 1LSB Step
(Note 8)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
4.8
2.7
4.8
5.2
s
Voltage Output Slew Rate
0.8
V/s
Capacitive Load Driving
1000
pF
Glitch Impulse
At Mid-Scale Transition
12
nV s
Multiplying Bandwidth
180
kHz
en
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
VP-P
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Inferred from measurement at code kL (Note 2) and at full scale.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2607/LTC2607-1,
LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.
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