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參數(shù)資料
| 型號(hào)： | DC777A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2601 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC777A Design File DC777A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 設(shè)置時(shí)間： | 10µs |
| DAC 型： | 電壓 |
| 工作溫度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2601 |
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LTC2601/LTC2611/LTC2621
9
2601fb
PIN FUNCTIONS
SDO (Pin 1): Serial Interface Data Output. This pin is used
for daisy-chain operation. The serial output of the shift
register appears at the SDO pin. The data transferred to
the device via the SDI pin is delayed 32 SCK rising edges
before being output at the next falling edge. SDO is an
active output and does not go high impedance even when
CS/LD is taken to a logic high level.
SDI (Pin 2): Serial Interface Data Input. Data is applied
to SDI for transfer to the device at the rising edge of SCK
(Pin 3). The LTC2601 accepts input word lengths of either
24 or 32 bits.
SCK (Pin 3): Serial Interface Clock Input. CMOS and TTL
compatible.
CLR (Pin 4): Asynchronous Clear Input. A logic low at this
level-triggered input clears all registers and causes the
DAC voltage outputs to drop to 0V for LTC2601/LTC2611/
LTC2621. A logic low at this input sets all registers to
midscale code and causes the DAC voltage outputs to go
to midscale for LTC2601-1/LTC2611-1/LTC2621-1. CMOS
and TTL compatible.
CS/LD (Pin 5): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specied command (see Table 1) is
executed.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT (Pin 7): DAC Analog Voltage Output. The output
range is 0V to VREF.
GND (Pin 8): Analog Ground.
VCC (Pin 9): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.
LDAC (Pin 10): Asynchronous DAC Update Pin. If CS/LD
is high, a falling edge on LDAC immediately updates the
DAC register with the contents of the input register (similar
to a software update). If CS/LD is low when LDAC goes
low, the DAC register is updated after CS/LD returns high.
A low on the LDAC pin powers up the DAC. A software
power down command is ignored if LDAC is low.
Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.
TYPICAL PERFORMANCE CHARACTERISTICS
Short-Circuit Output Current vs
VOUT (Sinking)
Short-Circuit Output Current vs
VOUT (Sourcing)
LTC2601/LTC2611/LTC2621
1V/DIV
0
10mA/DIV
10
20
30
40
50
1
23
4
2601 G15
56
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
1V/DIV
0
–50
10mA/DIV
–40
–30
–20
–10
0
1
23
4
2601 G16
56
VCC = 5.5V
VREF = 5.6V
CODE = FULL SCALE
VOUT SWEPT VCC TO 0V
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