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參數(shù)資料
型號: DC1384A-A
廠商: Linear Technology
文件頁數(shù): 22/22頁
文件大?。?/td> 0K
描述: BOARD DELTA SIGMA ADC LTC2452
軟件下載: QuikEval System
設(shè)計(jì)資源: DC1384A Design File
DC1384A Schematic
標(biāo)準(zhǔn)包裝: 1
系列: QuikEval™
ADC 的數(shù)量: 2
位數(shù): 16
采樣率(每秒): 60
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: ±VREF
已用 IC / 零件: LTC2452
已供物品:
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LTC2452
9
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
Figure 4. Data Output Timing
D15
LSB
SDO
SCK
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D0
D1
2452 F04
t1
t3
tKQ
tlSCK
thSCK
t2
CS
MSB
with the most significant bit of the result being present at
the SDO output pin (SDO = D15) once CS goes low. A new
data bit appears at the SDO output pin after each falling
edge detected at the SCK input pin. The output data can be
reliably latched by the user using the rising edge of SCK.
Conversion Status Monitor
For certain applications, the user may wish to monitor
the LTC2452 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 5.
Conversion status monitoring, while possible, is not re-
quiredforLTC2452asitsconversiontimeisfixedandequal
at approximately 16.6ms (23ms maximum). Therefore,
externaltimingcanbeusedtodeterminethecompletionofa
conversion cycle.
SERIAL INTERFACE
The LTC2452 transmits the conversion result and receives
the start of conversion command through a synchronous
3-wire interface. This interface can be used during the
CONVERT and SLEEP states to assess the conversion
status and during the DATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1) The LTC2452 functions with SCK idle high (commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
Figure 5. Conversion Status Monitoring Mode
SLEEP
t1
t2
SDO
SCK = HIGH
CONVERT
2452 F05
CS
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