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參數(shù)資料
| 型號： | DC1384A-A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2452 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1384A Design File DC1384A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 60 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | ±VREF |
| 已用 IC / 零件： | LTC2452 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2452ITS8#TRPBF-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452ITS8#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452IDDB#TRPBF-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452IDDB#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452CTS8#TRPBF-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452CTS8#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452CDDB#TRPBF-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452CDDB#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 8-DFN |
LTC2452
6
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
block DiagraM
pin FuncTions
SCK (Pin 1): Serial Clock Input. SCK synchronizes the
serial data output. While digital data is available (the ADC
is not in CONVERT state) and CS is LOW (ADC is not in
SLEEP state) a new data bit is produced at the SDO output
pin following every falling edge applied to the SCK pin.
GND (Pin 2): Ground. Connect to a ground plane through
a low impedance connection.
REF (Pin 3): Reference Input. The voltage on REF can have
any value between 2.5V and VCC. The reference voltage
sets the full-scale range.
VCC (Pin 4): Positive Supply Voltage. Bypass to GND
(Pin 2) with a 10F capacitor in parallel with a low-series-
inductance0.1FcapacitorlocatedasclosetotheLTC2452
as possible.
IN– (Pin 5), IN+ (Pin 6): Differential Analog Input.
CS (Pin 7): Chip Select (Active LOW) Digital Input. A LOW
on this pin enables the SDO digital output. A HIGH on this
pin places the SDO output pin in a high impedance state.
SDO (Pin 8): Three-State Serial Data Output. SDO is used
for serial data output during the DATA OUTPUT state and
can be used to monitor the conversion status.
Exposed Pad (Pin 9): Ground. Must be soldered to PCB
ground. For prototyping purposes, this pad may remain
floating.
Figure 1. Functional Block Diagram
16-BIT ΔΣ
A/D CONVERTER
DECIMATING
SINC FILTER
SCK
REF
VCC
GND
IN+
IN–
SDO
CS
2452 BD
–
16-BIT ΔΣ
A/D CONVERTER
SPI
INTERFACE
INTERNAL
OSCILLATOR
3
4
7
8
1
2, 9
6
5
CONVERTER OPERATION
Converter Operation Cycle
The LTC2452 is a low power, fully differential, delta-sigma
analog-to-digital converter with a simple 3-wire SPI in-
terface (see Figure 1). Its operation is composed of three
successive states: CONVERT, SLEEP and DATA OUTPUT.
The operating cycle begins with the CONVERT state, is
followed by the SLEEP state, and ends with the DATA OUT-
PUT state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK), and the
active low chip select input (CS).
TheCONVERTstatedurationisdeterminedbytheLTC2452
conversion time (nominally 16.6 milliseconds). Once
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