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參數(shù)資料
| 型號： | DC1278A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC2351-14 |
| 軟件下載： | QuikEval II System |
| 設(shè)計資源： | DC1278A Design File DC1278A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 16.5mW @ 1.5MSPS |
| 已用 IC / 零件： | LTC2351-14 |
| 已供物品： | 板 |
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LTC2351-14
4
235114fb
POWER REQUIREMENTS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. VDD = VCC = 3V.
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
The
l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD, VCC
Supply Voltage
2.7
3
3.6
V
IDD + ICC
Supply Current
Active Mode, fSAMPLE = 1.5Msps
Nap Mode
Active Mode, fSAMPLE = 1.5Msps (LTC2351H-14)
Nap Mode (LTC2351H-14)
Sleep Mode
l
5.5
1.5
6
1.8
4
8
2
9
2.5
15
mA
μA
PD
Power Dissipation
Active Mode with SCK, fSAMPLE = 1.5Msps
16.5
mW
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX) Maximum Sampling Rate per Channel
(Conversion Rate)
l
250
kHz
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period)
l
4μs
tSCK
Clock Period
(Note 16)
l
40
10000
ns
tCONV
Conversion Time
(Notes 6, 17)
96
SCLK cycles
t1
Minimum High or Low SCLK Pulse Width
(Note 6)
2
ns
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
10000
ns
t3
SCK Before CONV
(Note 6)
0
ns
t4
Minimum High or Low CONV Pulse Width
(Note 6)
4
ns
t5
SCK
↑ to Sample Mode
(Note 6)
4
ns
t6
CONV
↑ to Hold Mode
(Notes 6, 11)
1.2
ns
t7
96th SCK
↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
8
ns
t9
SCK
↑ to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t11
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specications apply for a single-ended CH0– CH5+
input with CH0– – CH5– grounded and using the internal 2.5V reference.
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
μA
CIN
Digital Input Capacitance
5pF
VOH
High Level Output Voltage
VDD = 3V, IOUT = –200μA
l
2.5
2.9
V
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT= 160μA
VDD = 2.7V, IOUT = 1.6mA
l
0.05
0.4
V
IOZ
Hi-Z Output Leakage DOUT
VOUT = 0V and VDD
l
±10
μA
COZ
Hi-Z Output Capacitance DOUT
1pF
ISOURCE
Output Short-Circuit Source Current
VOUT = 0V, VDD = 3V
20
mA
ISINK
Output Short-Circuit Sink Current
VOUT = VDD = 3V
15
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specications which apply over the
full operating temperature range, otherwise specications are at TA = 25°C. VDD = VCC = 3V.
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