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參數(shù)資料
| 型號(hào)： | DC1278A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC2351-14 |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1278A Design File DC1278A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 16.5mW @ 1.5MSPS |
| 已用 IC / 零件： | LTC2351-14 |
| 已供物品： | 板 |
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LTC2351-14
18
235114fb
235114 F07
3
30
32
1
2
3-WIRE SERIAL
INTERFACE LINK
OVDD
CONV
SCK
LTC2351-14
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
OGND
31
DGND
CONV
0V TO 3V LOGIC SWING
CLK
5V
3V
B13
B12
APPLICATIONS INFORMATION
HARDWARE INTERFACE TO TMS320C54x
The LTC2351-14 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 1.5Msps conversion rate of the
LTC2351-14. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC2351-14
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC2351-14. This conguration
is adequate to traverse a typical system board, but source
resistors at the buffer outputs and termination resistors
at the DSP, may be needed to match the characteristic
impedance of very long transmission lines. If you need
to terminate the SDO transmission line, buffer it rst with
one or two 74ACxx gates. The TTL threshold inputs of the
DSP port respond properly to the 3V swing used with the
LTC2351-14.
Figure 7. DSP Serial Interface to TMS320C54x
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