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參數(shù)資料
| 型號(hào)： | DC1082A-D |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 15/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1403A |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1082A Design File DC1082A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 0 ~ 2.5 V |
| 已用 IC / 零件： | LTC1403 |
| 已供物品： | 板 |
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LTC1403/LTC1403A
4
1403fb
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Supply Voltage
2.7
3.6
V
IDD
Positive Supply Voltage
Active Mode
Active Mode (LTC1403H, LTC1403AH)
Nap Mode
Nap Mode (LTC1403H, LTC1403AH)
Sleep Mode (LTC1403, LTC1403H)
Sleep Mode (LTC1403A, LTC1403AH)
●
4.7
5.2
1.1
1.2
2
7
8
1.5
1.8
15
10
mA
μA
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
12
mW
The ● denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 17)
POWER REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel (Conversion Rate)
●
2.8
MHz
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period)
●
357
ns
tSCK
Clock Period
(Notes 16)
●
19.8
10000
ns
tCONV
Conversion Time
(Note 6)
16
18
SCLK cycles
t1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
ns
t1
CONV to SCK Setup Time
(Notes 6, 10)
3
ns
t3
Nearest SCK Edge Before CONV
(Note 6)
0
ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t5
SCK to Sample Mode
(Note 6)
4
ns
t6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t7
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 13
(Notes 6, 12)
8
ns
t9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
The ● denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. VDD = 3V
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device reliability
and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and full-scale specications are measured for a single-ended
AIN+ input with AIN– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
dened as the deviation of a code from the straight line passing through the
actual endpoints of a transfer curve. The deviation is measured from the
center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is dened for the voltage difference between
AIN+ and AIN–.
Note 9: The absolute voltage at AIN+ and AIN– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when running
the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming out
into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.
Note 17: VDD = 3V, fSAMPLE = 2.8Msps.
Note 18: The LTC1403A is measured and specied with 14-bit Resolution
(1LSB = 152μV) and the LTC1403 is measured and specied with 12-bit
Resolution (1LSB = 610μV).
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