參數(shù)資料
型號: DAC5674IPHPRG4
廠商: Texas Instruments
文件頁數(shù): 14/39頁
文件大小: 0K
描述: IC DAC 14BIT 400MSPS 48-HTQFP
產(chǎn)品培訓模塊: Data Converter Basics
標準包裝: 1,000
系列: CommsDAC™
設置時間: 20ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-HTQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 400M
配用: 296-30860-ND - EVAL MODULE FOR DAC5674
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
21
PFD
ref
ICO
Fref
Fvco
LPF
R
C1
C2
DAC5674
External Loop Filter
PN
Figure 22. PLL Functional Block Diagram
Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters
N(1)
PHASE MARGIN (DEGREES)
BANDWIDTH (MHZ)
2
60
1.6
4
71
1.4
8
77
1
16
78
0.7
32
74
0.4
(1) N is the VCO divide-down factor from prescale and interpolation.
Non-Harmonic Clock-Related Spurious Signals
In interpolating DACs, imperfect isolation between the digital and DAC clock circuits generates spurious signals
at frequencies related to the DAC clock rate. The digital interpolation filters in these DACs run at subharmonic
frequencies of the output rate clock, where these frequencies are fDAC/2 , N = 1,2. For example, for 2×
interpolation only one interpolation filter runs at fDAC/2; for 4× interpolation, on the other hand, two interpolation
filters run at fDAC/2 and fDAC/4. These lower-speed clocks for the interpolation filter mix with the DAC clock
circuit and create spurious images of the wanted signal and second Nyquist-zone image at offsets of fDAC/2N.
Figure 23 shows the location of the largest spurious signals for 4
× interpolation for a real signal. With a real
output signal, there is no distinction between negative and positive frequencies, and therefore the signals that
appear at negative frequencies wrap and potentially fall near the wanted signal. In particular, at IFs near fDAC/8,
fDAC/4, and fDAC × 3/4 (50 MHz, 100 MHz, and 150 MHz in this example), the mixing effect results in spurious
signals falling near the wanted signal, which may present a problem depending on the system application. For
a frequency-symmetric signal (such as a single WCDMA or CDMA carrier), operating at exactly fDAC/8, fDAC/4
and fDAC × 3/4, the spurious signal falls completely inside the wanted signal, which produces a clean spectrum
but may result in degradation of the signal quality.
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