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參數(shù)資料
| 型號： | DAC1627D1G25HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating |
| 封裝： | DAC1627D1G25HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 896K |
| 代理商： | DAC1627D1G25HN |
www.nxp.com
2011 NXP Semiconductors N.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Date of release: April 2011
Document order number: 9397 750 17102
Printed in the Netherlands
An`inverse`(sin`x)`/`x`function`ensures`controlled`flatness``
(±0.5`dB`over`a`200`MHz`band`at`1`Gsps)`at`the`DAC`output.`
Multiple`Device`Synchronization`(MDS)`allows`synchronization`
of`the`DAC`outputs`of`multiple`DAC`devices.`MDS,`which`is`
a`feature`of`NXP’s`CGV`and`CGVxpress`technology`offering,`
guarantees`a`maximum`skew`of`one`output`clock`period`between`
several`devices.
The`DAC1627D1G25`also`includes`a`very`low`noise`capacitor-free`
integrated`Phase`Locked`Loop`(PLL),`which`generates`the`DAC`
clock`rate`from`the`LVDS`clock`rate.`This`internal`PLL`can`also`be`
bypassed`to`achieve`outstanding`performance:
The`DAC1627D1G25`includes`a`Low`Voltage`Differential`Signaling`
(LVDS)`Double`Data`Rate`(DDR)`receiver`interface,`with`on-chip`
100`Ω`termination,`that`allows`a`high`data`bandwidth`(312.5`MS/
sec)`at`the`input.`The`LVDS`DDR`interface`accepts`an`interleaved`
or`folded`input`data`stream,`programmed`via`a`Serial`Peripheral`
Interface`(SPI).`Interface`robustness`and`stability`is`ensured`by`an`
internal`LVDS`input`auto`calibration.
The`DAC1627D1G25`is`housed`in`a`small,`72-pin`HVQFN`package`
(10`x`10`mm`outline),`and`is`supported`by`demo`boards.
DAC1627D1G25 block diagram
Family
Type
Description
LVCMOS
LVDS/
DDR
CGV
TM
Supply
voltage (V)
Power Dissipation
per channel (mW)
SFDR
(dBc)
Interpolation
Package
DAC1627D1G25
DAC1627D1G25
Dual`16-bit`DAC`1.25`Gsps
-
-
1.8`/`3.3
885
85
2x,`4x,`8x
HVQFN72
DAC1617D1G0
DAC1617D1G0
Dual`16-bit`DAC`1.0`Gsps
-
-
1.8`/`3.3
660
79
2x,`4x,`8x
HVQFN72
Type
Related demoboard
Description
DAC1627D1G25
DAC1627D1G25/DB
DAC1627D1G25`demo`board;`LVDS`DDR`inputs
DAC1627D1G25IQMOD/DB
DAC1627D1G25`+`BGX7100`IQMod`demo`board;`LVDS`DDR`inputs
DAC1627D1G25 DAC and
BGX7100 IQMod evaluation board
DAC1627D1G25 DAC evaluation
board
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC1627D1G25 | |
| DAC1627D1G25HN | Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating |
| DAN2222E | SWITCHING DIODE |
| DCX100NS | 100mA DUAL COMPLEMENTARY PRE-BIASED TRANSISTORS |
| DCX100NS-7 | 100mA DUAL COMPLEMENTARY PRE-BIASED TRANSISTORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1627D1G25HN/C1, | 功能描述:調(diào)節(jié)器/解調(diào)器 DUAL 16b 1.25GSPS to 1.25 Gsps RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| DAC1627D1G25HN/C1,551 | 功能描述:調(diào)節(jié)器/解調(diào)器 Dual 16-bit DAC, up to 1.25 Gsps RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| DAC1627D1G25HN-C1 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1627D1G25HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Tape and Reel |
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