參數(shù)資料
型號: DAC1405D650HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 14-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
封裝: DAC1405D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1405D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁數(shù): 11/45頁
文件大小: 1033K
代理商: DAC1405D650HW
DAC1405D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 10 September 2010
11 of 45
NXP Semiconductors
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2
×
, 4
×
and 8
×
interpolating
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
O(aux)
auxiliary output current
V
O(aux)
auxiliary output voltage
N
DAC(aux)mono
auxiliary DAC
monotonicity
Input timing (see
Figure 10
)
f
data
data rate
t
w(CLK)
CLK pulse width
t
h(i)
input hold time
t
su(i)
input set-up time
Output timing
f
s
sampling frequency
t
s
settling time
NCO frequency range; f
s
= 640 Msps
f
NCO
NCO frequency
differential outputs
compliance range
guaranteed
I
C
D
-
0
-
2.2
-
10
-
2
-
mA
V
bit
Dual-port mode input
C
C
C
C
-
1.5
1.1
1.1
-
-
-
-
160
T
data
1.5
-
-
MHz
ns
ns
ns
C
D
-
-
-
20
650
-
Msps
ns
to
±
0.5 LSB
register value = 00000000h
register value = FFFFFFFFh
D
D
D
-
-
-
0
640
0.149 -
-
-
MHz
MHz
Hz
f
step
Low-power NCO frequency range; f
DAC
= 640 MHz
f
NCO
NCO frequency
step frequency
register value = 00000000h
register value = F8000000h
D
D
D
-
-
-
0
620
20
-
-
-
MHz
MHz
MHz
f
step
Dynamic performance; PLL on
SFDR
spurious-free dynamic
range
step frequency
f
data
= 80 MHz; f
s
= 320 Msps; BW = f
data
/ 2
f
o
= 35 MHz at 0 dBFS
f
data
= 80 MHz; f
s
= 640 Msps; BW = f
data
/ 2
f
o
= 4 MHz at 0 dBFS
f
o
= 19 MHz at 0 dBFS
f
data
= 160 MHz; f
s
= 640 Msps; BW = f
data
/ 2
f
o
= 70 MHz at 0 dBFS
f
s
= 640 Msps; f
o
= 96 MHz at 0 dBFS
2.51 MHz
f
offset
2.71 MHz;
B = 30 kHz
2.71 MHz
f
offset
3.51 MHz;
B = 30 kHz
3.51 MHz
f
offset
4 MHz;
B = 30 kHz
4 MHz
f
offset
40 MHz;
B = 1 MHz
C
-
84
-
dBc
I
I
-
-
77
76
-
-
dBc
dBc
C
-
84
-
dBc
SFDR
RBW
restricted bandwidth
spurious-free dynamic
range
I
-
93
86
dBc
I
-
92
-
dBc
I
93
88
dBc
I
-
85
72
dBc
Table 5.
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together; T
amb
=
40
°
C to
+85
°
C; typical values measured at T
amb
= 25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Test
[1]
Min
Typ
Max
Unit
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