參數(shù)資料
型號(hào): DAC1405D650HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 14-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
封裝: DAC1405D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1405D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁(yè)數(shù): 10/45頁(yè)
文件大?。?/td> 1033K
代理商: DAC1405D650HW
DAC1405D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 10 September 2010
10 of 45
NXP Semiconductors
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2
×
, 4
×
and 8
×
interpolating
Clock inputs (CLKP and CLKN)
[2]
V
i
input voltage
V
idth
input differential
threshold voltage
R
i
input resistance
C
i
input capacitance
Digital inputs (I0 to I13, Q0 to Q13)
V
IL
LOW-level input voltage
V
IH
HIGH-level input
voltage
I
IL
LOW-level input current V
IL
= 1.0 V
I
IH
HIGH-level input
current
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
V
IL
LOW-level input voltage
V
IH
HIGH-level input
voltage
I
IL
LOW-level input current V
IL
= 1.0 V
I
IH
HIGH-level input
current
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
I
O(fs)
full-scale output current register value = 00h
CLKP; or CLKN
|
V
gpd
|
< 50 mV
|
V
gpd
|
< 50 mV
C
C
[3]
825
-
-
1575
+100
mV
mV
[3]
100
D
D
-
-
10
0.5
-
-
M
Ω
pF
C
C
GNDIO -
2.3
1.0
V
DD(IO)(3V3)
V
V
-
I
I
-
-
60
80
-
-
μ
A
μ
A
V
IH
= 2.3 V
C
C
GNDIO -
2.3
1.0
V
DD(IO)(3V3)
V
V
-
I
I
-
-
20
20
-
-
nA
nA
V
IH
= 2.3 V
C
C
C
D
D
D
C
C
-
-
1.8
-
-
-
-
-
1.6
20
-
250
3
8
6
18
-
-
V
DDA(3V3)
-
-
-
-
-
mA
mA
V
k
Ω
pF
bit
ppm/
°
C
ppm/
°
C
default register
compliance range
V
O
R
o
C
o
N
DAC(mono)
Δ
E
O
Δ
E
G
Reference voltage output (GAPOUT)
V
O(ref)
reference output
voltage
Δ
V
O(ref)
reference output
voltage variation
I
O(ref)
reference output
current
output voltage
output resistance
output capacitance
DAC monotonicity
offset error variation
gain error variation
guaranteed
T
amb
= 25
°
C
I
1.2
1.25
1.29
V
C
-
117
-
ppm/
°
C
external voltage 1.25 V
D
-
40
-
μ
A
Table 5.
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together; T
amb
=
40
°
C to
+85
°
C; typical values measured at T
amb
= 25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA; maximum sample rate; PLL on unless otherwise
specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Test
[1]
Min
Typ
Max
Unit
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