參數(shù)資料
型號(hào): DAC1405D650HW
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): DAC
英文描述: Dual 14-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
文件頁(yè)數(shù): 35/45頁(yè)
文件大小: 1033K
代理商: DAC1405D650HW
DAC1405D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 10 September 2010
35 of 45
NXP Semiconductors
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2
×
, 4
×
and 8
×
interpolating
Figure 18
provides an example of a DC interface with the auxiliary DACs to an AQM with
a 3.3 V
i(cm)
common mode input level.
The constraints to adjust the interface are the output compliance range of the DAC and
the auxiliary DACs, the input common mode level of the AQM, and the range of offset
correction.
Fig 17. An example of a DC interface to a 1.7 V
i(cm)
AQM when using auxiliary DACs
Fig 18. An example of a DC interface to a 3.3 V
i(cm)
AQM when using auxiliary DACs
001aaj543
51.1
Ω
51.1
Ω
442
Ω
442
Ω
V
DDA(3V3)
IOUTnP
IOUTnN
0 mA to 20 mA
BBP
BBN
AQM (V
i(cm)
= 1.7 V)
698
Ω
698
Ω
51.1
Ω
51.1
Ω
AUXnP
AUXnN
1.1 mA (typ.)
(1)
IOUTnP/IOUTnN; V
o(cm)
= 2.67 V; V
o(dif)(p-p)
= 1.94 V
(2)
BBP/BBN; V
i(cm)
= 1.7 V; V
i(dif)(p-p)
= 1.23 V; offset correction up to 36 mV
(1)
(2)
001aaj544
54.9
Ω
54.9
Ω
237
Ω
237
Ω
3.3 V
IOUTnP
IOUTnN
AUXnP
AUXnN
BBP
BBN
AQM (V
i(cm)
= 3.3 V)
750
Ω
750
Ω
5 V
634
Ω
634
Ω
442
Ω
442
Ω
(1)
IOUTnP/IOUTnN; V
o(cm)
= 2.75 V; V
o(dif)(p-p)
= 1.96 V
(2)
BBP/BBN; V
i(cm)
= 3.3 V; V
i(dif)(p-p)
= 1.5 V; offset correction up to 36 mV
(1)
(2)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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