參數(shù)資料
型號: DAC1405D650HW
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 14-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
文件頁數(shù): 22/45頁
文件大?。?/td> 1033K
代理商: DAC1405D650HW
DAC1405D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 10 September 2010
22 of 45
NXP Semiconductors
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2
×
, 4
×
and 8
×
interpolating
Table 28.
Bit
7 to 0
Table 29.
Default settings are shown highlighted.
Bit
Symbol
7
AUX_B_PD
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see
Table 10 on page 17
) and it
defines whether the DAC1405D650 operates in the Dual-port mode or in the Interleaved
mode (see
Table 30
).
Table 30.
Bit 3 setting
0
1
10.3.1
Dual-port mode
The data input for Dual-port mode operation is shown in
Figure 5 “Dual-port mode”
. Each
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
10.3.2
Interleaved mode
The data input for the Interleaved mode operation is illustrated by
Figure 6 “Interleaved
mode operation”
.
DAC_B_Aux_MSB register (address 1Ch) bit description
Symbol
Access
AUX_B[9:2]
R/W
Value
-
Description
most significant 8-bits for the auxiliary
DAC B
DAC_B_Aux_LSB register (address 1Dh) bit description
Access
R/W
Value
Description
auxiliary DAC B power
on
off
lower 2-bits for the auxiliary DAC B
0
1
1 to 0
AUX_B[1:0]
R/W
Mode selection
Function
Dual port mode
Interleaved mode
I13 to I0
active
active
Q13 to Q0
active
off
Pin 41
Q13
SELIQ
Fig 5.
Dual-port mode
001aaj585
LATCH
I
2
×
2
×
2
×
In
FIR 1
FIR 1
FIR 2
FIR 2
FIR 3
FIR 3
LATCH
Q
2
×
2
×
2
×
Qn
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相關代理商/技術參數(shù)
參數(shù)描述
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