參數(shù)資料
型號: DAC1401D125HL
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 14-bit DAC, up to 125 Msps
中文描述: PARALLEL, WORD INPUT LOADING, 0.043 us SETTLING TIME, 14-BIT DAC, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC. LQFP-48
文件頁數(shù): 15/25頁
文件大?。?/td> 359K
代理商: DAC1401D125HL
DAC1401D125_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
15 of 25
NXP Semiconductors
DAC1401D125
Dual 14-bit DAC, up to 125 Msps
10.2.1
Dual port mode
The data and clock circuit for Dual port mode operation is shown in
Figure 14
.
Each DAC has its own independent data and clock inputs. The data enters the input latch
on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The
output is updated on the rising edge of the CLKA/CLKB signal.
10.2.2
Interleaved mode
The data and clock circuit for Interleaved mode operation is illustrated in
Figure 16
.
Table 6.
Mode Function
0
Interleaved mode
1
Dual port mode
Mode selection
DA13 to DA0 DB13 to DB0
active
active
Pin 17
IQWRT
WRTA
Pin 18
IQCLK IQRESET
CLKA
CLKB
Pin 19
Pin 20
IQSEL
WRTB
off
active
Fig 14. Dual port mode operation
Fig 15. Dual port mode timing
14
14
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DA13 to DA0
WRTA
WRTB
CLKA
CLKB
INPUT A
LATCH
DAC A
LATCH
14
14
DB13 to DB0
INPUT B
LATCH
DAC B
LATCH
001aai939
DA13 to DA0/
DB13 to DB0
N
N+1
N
2
N
1
N
N+1
N+2
N+2
N+3
WRTA/
WRTB
CLKA/
CLKB
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
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