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| 型號： | DAC1205D750HW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 12-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating |
| 封裝： | DAC1205D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1205D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 352K |
| 代理商： | DAC1205D750HW |
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DAC1205D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
25 of 42
NXP Semiconductors
DAC1205D750
Dual 12-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.5.1
Timing when using the internal PLL (PLL on)
In
Table 33
, the links between internal and external clocking are defined. The setting
applied to PLL_DIV[1:0] (register 02h[4:3]; see
Table 9 “Register allocation map”
) allows
the frequency between the digital part and the DAC core to be adjusted.
Table 33.
Mode
The settings applied to DAC_CLK_DELAY[1:0] (register 02h[2:1]) and DAC_CLK_POL
(register 02h[0]), allow adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in
Table 34
.
Table 34.
Mode
10.5.2
Timing when using an external PLL (PLL off)
It is recommended that a delay of 280 ps is used on the internal digital clock (CLK
dig
) to
obtain optimum device performance up to750 Msps.
Table 35.
Address
Dec
2
10.6 FIR filters
The DAC1205D750 integrates three selectable Finite Impulse Response (FIR) filters
which enables the device to use 4
or 8
interpolation rates. All three interpolation filters
have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than
0.0005 dB. The coefficients of the interpolation filters are given in
Table 36 “Interpolation
filter coefficients”
.
Fig 10. Input timing diagram when internal PLL bypassed (off)
001aam197
N
t
su(i)
90 %
50 %
90 %
I11 to I0/
Q11 to Q0
SYNC
(SYNCP
SYNCN)
t
h(i)
N + 1
N + 2
Frequencies
CLK input
(MHz)
185
92.5
370
185
Input data rate
(MHz)
185
92.5
370
185
Interpolation
Update rate
(Msps)
740
740
740
740
PLL_DIV[1:0]
Dual Port
Dual Port
Interleaved
Interleaved
4
8
4
8
01 (/ 4)
10 (/ 8)
00 (/ 2)
01 (/ 4)
Sample clock phase and polarity examples
Input data rate
(MHz)
92.5
92.5
Interpolation
Update rate
(Msps)
370
740
DAC_CLK_
DELAY [1:0]
01
01
DAC_CLK_
POL
0
0
Dual Port
Dual Port
4
8
Optimum external PLL timing settings
Register name
Hex
02h
PLLCFG
Value
Digital clock delay Bin
280 ps
Dec
136
Hex
88h
10001000
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| DAC1205D750HW/C1,5 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 12BIT DAC 750MSPS RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1208 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit, uP Compatible, Double-Buffered D to A Converters |
| DAC1208D650 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface |
| DAC1208D650HN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface |
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