參數(shù)資料
型號: DAC1205D650HW
廠商: NXP Semiconductors N.V.
元件分類: 外設及接口
英文描述: Dual 12-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating
封裝: DAC1205D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1205D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁數(shù): 40/43頁
文件大小: 295K
代理商: DAC1205D650HW
DAC1205D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 13 September 2010
40 of 43
NXP Semiconductors
DAC1205D650
Dual 12-bit DAC, up to 650 Msps; 2
×
4
×
and 8
×
interpolating
13. Glossary
Spurious-Free Dynamic Range (SFDR): —
The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
Intermodulation Distortion (IMD): —
From a dual-tone digital input sine wave (these
two frequencies being close together), the intermodulation distortion products IMD2 and
IMD3 (respectively, 2
nd
and 3
rd
order components) are defined below.
IMD2 —
The ratio of the RMS value of either tone to the RMS value of the worst 2
nd
order
intermodulation product.
IMD3 —
The ratio of the RMS value of either tone to the RMS value of the worst 3
rd
order
intermodulation product.
Restricted Bandwidth Spurious-Free Dynamic Range —
The ratio of the RMS value of
the reconstructed output sine wave to the RMS value of the noise, including the
harmonics, in a given bandwidth centered around f
offset
.
14. Revision history
Table 42.
Document ID
DAC1205D650 v.2
Modifications:
Revision history
Release date
20100913
Figure 18
corrected the value of the resistors on pin AUXnP
20090728
Product data sheet
Data sheet status
Product data sheet
Change notice
-
Supersedes
DAC1205D650 v.1
DAC1205D650 v.1
-
-
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