參數(shù)資料
型號: DAC1201D125HL
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC, up to 125 Msps
封裝: DAC1201D125HL/C1<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;DAC1201D125HL/C1<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2
文件頁數(shù): 16/26頁
文件大?。?/td> 274K
代理商: DAC1201D125HL
DAC1201D125_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 27 November 2008
16 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.2.2
Interleaved mode
The data and clock circuit for Interleaved mode operation is illustrated in
Figure 16
.
In Interleaved mode, both DACs use the same data and clock inputs at twice the update
rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A
or latch B, depending on the value of IQSEL. The IQSEL transition must occur when
IQWRT and IQCLK are LOW.
The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is
updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see
Figure 17
.
Fig 16. Interleaved mode
Fig 17. Interleaved mode timing
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÷
2
12
12
DA11 to DA0
IQWRT
IQSEL
IQCLK
IQRESET
INPUT A
LATCH
DAC A
LATCH
12
12
INPUT B
LATCH
DAC B
LATCH
001aaj116
DA11 to DA0/
DB11 to DB0
N
N+1
XX
XX
N+1
N
N+3
N+5
N+2
N+4
N+2
IQRESET
IOUTAP, IOUTAN
IOUTBP, IOUTBN
N+3
N+4
N+5
N+6
N+7
IQSEL
IQWRT
IQCLK
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DAC1201D125HL/C1'1 制造商:Integrated Device Technology Inc 功能描述:IC DAC 12BIT 125MSPS DL 48LQFP
DAC1201D125HL/C1,1 功能描述:數(shù)模轉(zhuǎn)換器- DAC DAC 2-CH Segment 12-Bit RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1201D125HL/C1,118 制造商:NXP Semiconductors 功能描述:
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