參數(shù)資料
型號: DAC1201D125HL
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC, up to 125 Msps
中文描述: 12-BIT DAC, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, HTQFP-48
文件頁數(shù): 15/26頁
文件大?。?/td> 274K
代理商: DAC1201D125HL
DAC1201D125_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 27 November 2008
15 of 26
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.2.1
Dual-port mode
The data and clock circuit for Dual-port mode operation is shown in
Figure 14
.
Each DAC has its own independent data and clock inputs. The data enters the input latch
on the rising edge of the WRTA/WRTB signal and is transferred to the DAC latch. The
output is updated on the rising edge of the CLKA/CLKB signal.
Table 6.
Mode Function
LOW
Interleaved mode
HIGH Dual-port mode
Mode selection
DA11 to DA0 DB11 to DB0
active
active
Pin 17
IQWRT
WRTA
Pin 18
IQCLK IQRESET
CLKA
CLKB
Pin 19
Pin 20
IQSEL
WRTB
off
active
Fig 14. Dual-port mode operation
Fig 15. Dual-port mode timing
12
12
001aai977
DA11 to DA0
WRTA
WRTB
CLKA
CLKB
INPUT A
LATCH
DAC A
LATCH
12
12
DB11 to DB0
INPUT B
LATCH
DAC B
LATCH
001aaj115
DA11 to DA0/
DB11 to DB0
N
N+1
N
2
N
1
N
N+1
N+2
N+2
N+3
WRTA/
WRTB
CLKA/
CLKB
IOUTAP, IOUTAN/
IOUTBP, IOUTBN
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