5 FN6785.0 July 29, 2010 Analog Supply Pins (PLL) PLLVDD 1.7 1.8 1.9 V Active Current - 10 - mA Power-Down Current (Note 10)" />
參數(shù)資料
型號： D2-45157-QR-T
廠商： Intersil
文件頁數(shù)： 27/31頁
文件大?。?/td> 0K
描述： IC DGTL AMP PWM CTRLR 68QFN
標(biāo)準(zhǔn)包裝： 3,000
系列： D2Audio™
類型： D 類
輸出類型： 2 通道（立體聲）
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： 30W x 2 @ 8 歐姆
電源電壓： 9 V ~ 26 V
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
封裝/外殼： 68-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
D2-45057, D2-45157
5
FN6785.0
July 29, 2010
Analog Supply Pins (PLL)
PLLVDD
1.7
1.8
1.9
V
Active Current
-
10
-
mA
Power-Down Current
(Note 10)
-5
-
mA
CRYSTAL OSCILLATOR
Crystal Frequency (Fundamental Mode Crystal)
Xo
20
24.576
25
MHz
Duty Cycle
Dt
40
-
60
%
Start-up Time (Start-up Time is Oscillator Enabled
(with Valid Supply) to Stable Oscillation)
tSTART
-5
20
ms
PLL
VCO Frequency
FVCO
240
294.912
300
MHz
PLL Lock Time from any Input Change
-
3
-
ms
1.8V POWER-ON RESET
Reset Enabled Voltage Level
VEN
0.95
1.1
1.3
V
POR Minimum Output Pulse Width
tDIS
-5
-
s
1.8V BROWNOUT DETECTION
Detect Level
1.4
1.5
1.7
V
Pulse Width Rejection
tBOD1
-100
-
ns
Minimum Output Pulse Width
tO1
-20
-
ns
3.3V (PWMVDD) BROWNOUT DETECTION
Detect Level
2.5
2.7
2.9
V
Pulse Width Rejection
tBOD3
-100
-
ns
Minimum Output Pulse Width
tO3
-20
-
ns
GATE DRIVE INTERNAL +5V BROWN-OUT DETECTION
Gate Drive Supply Undervoltage Threshold
-
4.5
-
V
Gate Drive Supply Undervoltage Threshold Hysteresis
-
200
-
mV
Gate Drive Supply Undervoltage Threshold Glitch
Rejection
-50
-
ns
PROTECTION DETECT
High Voltage (+VDDHV) Undervoltage Protection
-
7
9
V
Overcurrent Trip Threshold
-4
-
A
Overcurrent De-glitch
-2.5
-
ns
Short-Circuit Current Limit (Peak)
-
8
-
A
Overcurrent Response Time
-20
-
ns
Thermal Shut-Down (Power Stages)
-
140
-
°C
Thermal Shut-Down Hysteresis (Power Stages)
-
30
-
°C
NOTES:
8. All input pins except XTALI.
9. Input leakage applies to all pins except XTALO.
10. Power-down is with device in reset and clocks stopped.
Electrical Specifications TA = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at
147.456MHz with typical audio data traffic. (Continued)
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
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