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D2-45057, D2-45157
7
FN6785.0
July 29, 2010
Two-Wire (I2C) Interface Port Timing TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
fSCL
SCL Frequency
-
100
kHz
tbuf
Bus Free Time Between Transmissions
4.7
-
s
twlowSCLx
SCL Clock Low
4.7
-
s
twhighSCLx
SCL Clock High
4.0
-
s
tsSTA
Setup Time For a (Repeated) Start
4.7
-
s
thSTA
Start Condition Hold Time
4.0
-
s
thSDAx
SDA Hold From SCL Falling (Note
11)1 (typical)
sys clk
tsSDAx
SDA Setup Time to SCL Rising
250
-
ns
tdSDAx
SDA Output Delay Time From SCL Falling
-
3.5
s
tr
Rise Time of Both SDA and SCL (Note
12)-
1
s
tf
Fall Time of Both SDA and SCL (Note
12)
-
300
ns
tsSTO
Setup Time For a Stop Condition
4.7
-
s
NOTES:
11. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
12. Limits established by characterization and not production tested.
twlowSCLx
SCLx
SDAx
(INPUT)
tsSTA
thSTAx
tr
tf
tsSDAx
thSDAx
tsSTO
tbuf
SDAx
(OUTPUT)
tdSDAx
twhighSCLx
FIGURE 2. I2C INTERFACE TIMING