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參數(shù)資料
| 型號： | CYW255OXC |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 255 SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | LEAD FREE, SSOP-48 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 129K |
| 代理商： | CYW255OXC |
W255
..........................Document #: 38-07255 Rev. *D Page 4 of 9
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN)............ –0.5V to VDD+0.5
Storage Temperature...................................–65°C to +150°C
Static Discharge Voltage .......................................... > 2000V
(per MIL-STD-883, Method 3015)
Operating Conditions[2]
Parameter
Description
Min.
Typ.
Max.
Unit
VDD3.3
Supply Voltage
3.135
3.465
V
VDD2.5
Supply Voltage
2.375
2.625
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
COUT
Output Capacitance
6
pF
CIN
Input Capacitance
5
pF
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VIL
Input LOW Voltage
For all pins except SMBus
0.8
V
VIH
Input HIGH Voltage
2.0
V
IIL
Input LOW Current
VIN = 0V
50
A
IIH
Input HIGH Current
VIN = VDD
50
A
IOH
Output HIGH Current
VDD = 2.375V
VOUT = 1V
–18
–32
mA
IOL
Output LOW Current
VDD = 2.375V
VOUT = 1.2V
26
35
mA
VOL
Output LOW Voltage[3]
IOL = 12 mA, VDD = 2.375V
0.6
V
VOH
Output HIGH Voltage[3]
IOH = –12 mA, VDD = 2.375V
1.7
V
IDD
Supply Current[3]
(DDR-only mode)
Unloaded outputs, 133 MHz
400
mA
IDD
Supply Current
(DDR-only mode)
Loaded outputs, 133 MHz
500
mA
IDDS
Supply Current
PWR_DWN# = 0
100
A
VOUT
Output Voltage Swing
See test circuity (refer to
0.7
VDD +0.6
V
VOC
Output Crossing Voltage
(VDD/2) –
0.1
VDD/2
(VDD/2) +
0.1
V
INDC
Input Clock Duty Cycle
48
52
%
Switching Characteristics [4]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
–
Operating Frequency
66
200
MHz
–
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs
INDC –
5%
INDC +
5%
%
t3
SDRAM Rising Edge Rate[3]
Measured between 0.4V and 2.4V
1.0
2.75
V/ns
t4
SDRAM Falling Edge Rate[3]
Measured between 2.4V and 0.4V
1.0
2.75
V/ns
t3d
DDR Rising Edge Rate[3]
Measured between 20% to 80% of
output (refer to Figure 1)
0.5
1.50
V/ns
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
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