- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223639 > CYW255OXC (SILICON LABORATORIES) 255 SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 PDF資料下載
參數(shù)資料
| 型號： | CYW255OXC |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 255 SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | LEAD FREE, SSOP-48 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 129K |
| 代理商： | CYW255OXC |
W255
..........................Document #: 38-07255 Rev. *D Page 2 of 9
Pin Summary
Pin Name
Pins
Pin Description
SEL_DDR
48
Input to configure for DDR-ONLY mode or STANDARD SDRAM
mode.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,
42, 43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM
output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,
43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM
mode.
SCLK
25
SMBus clock input
SDATA
24
SMBus data input
BUF_IN
13
Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V
input for STANDARD SDRAM mode.
FBOUT
1
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.
PWR_DWN#
36
Active LOW input to enable power-down mode; all outputs will be
pulled LOW.
DDR[6:11]T
28, 30, 34, 39, 43, 45
Clock outputs. These outputs provide copies of BUF_IN.
DDR[6:11]C
27, 29, 33, 38, 42, 44
Clock outputs. These outputs provide complementary copies of
BUF_IN.
DDR[0:5]T_SDRAM
[10,0,2,4,6,8]
4, 6, 10, 15, 19, 21
Clock outputs. These outputs provide copies of BUF_IN. Voltage swing
depends on VDD3.3_2.5 power supply.
DDR[0:5]C_SDRAM
[11,1,3,5,7,9]
5, 7, 11, 16, 20, 22
Clock outputs. These outputs provide complementary copies of
BUF_IN when SEL_DDR is active. These outputs provide copies of
BUF_IN when SEL_DDR is inactive. Voltage swing depends on
VDD3.3_2.5 power supply.
VDD3.3_2.5
2, 8, 12, 17, 23
Connect to 2.5V power supply when W255 is configured for
DDR-ONLY mode. Connect to 3.3V power supply, when W255 is
configured for standard SDRAM mode.
VDD2.5
32, 37, 41, 47
2.5V voltage supply
GND
3, 9, 14, 18, 26, 31, 35, 40, 46 Ground
相關PDF資料 |
PDF描述 |
|---|---|
| CYW256OXCT | 256 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| D01-9970121 | SIP1, IC SOCKET |
| D01-9974842 | SIP48, IC SOCKET |
| D03-28-T-A-A-2 | IC SOCKET |
| D03-28-T-B-B-1 | IC SOCKET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYW255OXCT | 功能描述:時鐘緩沖器 200MhZ-24 Out Buff 4 DDR3 SDRAM DIMMS RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYW256OXC | 功能描述:時鐘緩沖器 SDRAM & DDR Output Buff, W256 datasheet RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYW256OXCT | 功能描述:時鐘緩沖器 SDRAM & DDR Output Buff, W256 datasheet RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYW305OXC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Legacy-Sys Clk Intel RSolano Chip W305B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CYW305OXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Legacy-Sys Clk Intel RSolano Chip W305B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復。