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參數(shù)資料
| 型號(hào)： | CYM8301BV33 |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 335K |
| 代理商： | CYM8301BV33 |
CYM8301BV33
Document #: 38-05294 Rev. **
Page 4 of 9
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≤
3 ns
≤
3 ns
R1 317
R2
351
OUTPUT
R
L
= 50
Z
0
= 50
V
TH
= 1.5V
Switching Characteristics
[4]
Over the Operating Range
Parameter
Description
[2]
CYM8301BV-10
CYM8301BV-12
CYM8301BV-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
10
12
15
ns
t
AA
Address to Data Valid
10
12
15
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE active to Data Valid
10
12
15
ns
t
DOE
OE LOW to Data Valid
7
7.5
8.5
ns
t
LZOE
OE LOW to Low-Z
0
0
0
ns
t
HZOE
OE HIGH to High-Z
[5, 6]
CE Active to Low-Z
[6]
5
6
7
ns
t
LZCE
3
3
3
ns
t
HZCE
CE Inactive to High-Z
[5, 6]
5
6
7
ns
t
PU
CE Active to Power-up
0
0
0
ns
t
PD
Write Cycle
[7, 8]
CE Inactive to Power-down
10
12
15
ns
t
WC
Write Cycle Time
10
12
15
ns
t
SCE
CE active to Write End
9
9
9
ns
t
AW
Address Set-up to Write End
9
9
10
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
8
10
11
ns
t
SD
Data Set-up to Write End
6
6
7
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low-Z
[6]
3
3
3
ns
t
HZWE
WE LOW to High-Z
[5, 6]
5
6
7
ns
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
.
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
5.
6.
7.
8.
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