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參數(shù)資料
| 型號： | CYM8210BPM-70C |
| 英文描述： | x16 SRAM Module |
| 中文描述： | x16的SRAM模塊 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 106K |
| 代理商： | CYM8210BPM-70C |
CYM8210BPM
Document #: 38-05008 Rev. **
Page 4 of 8
Switching Characteristics
Over the Operating Range
[
3
]
70 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
4.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed by design and not 100% tested.
5.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
6.
The internal write time of the memory is defined by the overlap of E3/E2/E1/E0 LOW and WH/WL LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Description
Min.
Max.
Unit
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
E3/E2/E1/E0 LOW to Data Valid
G LOW to Data Valid
G LOW to Low Z
G HIGH to High Z
E3/E2/E1/E0 LOW to Low Z
[4]
E3/E2/E1/E0 HIGH to High Z
[4, 5]
E3/E2/E1/E0 HIGH to Power-Down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
70
Write Cycle Time
E3/E2/E1/E0 LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WH/WL Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WH/WL HIGH to Low Z
WH/WL LOW to High Z
[5]
70
60
60
0
0
55
25
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
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