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參數(shù)資料
| 型號(hào)： | CY7C1011CV33-15BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 128K x 16 Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 15 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | CY7C1011CV33-15BVI |
CY7C1011CV33
Document #: 38-05232 Rev. *C
Page 5 of 11
tSCE
CE LOW to Write End
7
8
10
ns
tAW
Address Set-up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-up to Write End
5
6
7
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low-Z[7]
333
ns
tHZWE
WE LOW to High-Z[6, 7]
56
7
ns
tBW
Byte Enable to End of Write
7
8
10
ns
AC Switching Characteristics Over the Operating Range (continued)[4]
Parameter
Description
-10
-12
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1[10, 11]
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
11. WE is HIGH for read cycle.
3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1011CV33-15ZC | 128K x 16 Static RAM |
| CY7C1011CV33-15ZI | 128K x 16 Static RAM |
| CY7C106B-12VC | 256K x 4 Static RAM |
| CY7C106B-15VC | 256K x 4 Static RAM |
| CY7C106B-15VI | 256K x 4 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1011CV33-15BVIT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY7C1011CV33-15Z | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1011CV33-15ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1011CV33-15ZI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 2M-Bit 128K x 16 15ns 44-Pin TSOP-II |
| CY7C1011CV33-15ZXC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 2M-Bit 128K x 16 15ns 44-Pin TSOP-II |
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