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參數(shù)資料
| 型號： | CY62167DV20 |
| 英文描述： | Memory |
| 中文描述： | 內存 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 153K |
| 代理商： | CY62167DV20 |
CY62147V18 MoBL2
4
.
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH
é
VENIN EQUIVALENT
R
TH
ALL INPUT PULSES
R1
V
CC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R1
R2
(a)
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
(C)
Parameters
R1
R2
R
TH
V
TH
1.8V
15294
11300
6500
0.85V
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.0
Typ.
[2]
Max.
1.95
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V
CE > V
CC
–
0.3V,
V
IN
> V
CC
–
0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+ 0.3V
Std.
10
25
t
CDR[3]
Chip Deselect to Data
Retention Time
0
ns
t
R[4]
Note:
4.
Operation Recovery Time
85
ns
Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 10
μ
s or stable at V
CC(min.)
>10
μ
s.
Data Retention Waveform
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
t
R
CE
V
CC
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62167DV20L-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA |
| CY62167DV20LL-55BVI | 制造商:Rochester Electronics LLC 功能描述:16M (1M X 16)- 2.0V SLOW ASYNCH SRAM - Bulk |
| CY62167DV20LL-5BVI | 制造商:Cypress Semiconductor 功能描述: |
| CY62167DV30L-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 16M-Bit 1M x 16 70ns 48-Pin VFBGA |
| CY62167DV30LL-45ZI | 制造商:Cypress Semiconductor 功能描述: |
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