參數(shù)資料
型號(hào): CY39100Z484-125BBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): PLD
英文描述: TRAN_GUARD,5.6WV,15.5VCLAMP,0.1J,0603
中文描述: LOADABLE PLD, 10 ns, PBGA484
封裝: 23 X 23 MM, 1.6 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁(yè)數(shù): 28/86頁(yè)
文件大小: 1212K
代理商: CY39100Z484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 28 of 86
Switching Waveforms
(continued)
Cluster Memory Synchronous Flow-Through Timing
GLOBAL
CLOCK
ADDRESS
WRITE
ENABLE
REGISTERED
INPUT
REGISTERED
OUTPUT
t
CLMS
t
CLMS
t
CLMS
t
CLMH
t
CLMH
t
CLMH
READ
WRITE
READ
t
CLMDV1
t
CLMDV1
t
CLMDV1
t
CLMCYC1
Cluster Memory Internal Clocking
MACROCELL
INPUT CLOCK
CLUSTER MEMORY
INPUT CLOCK
CLUSTER MEMORY
OUTPUT CLOCK
t
CLMMACS2
t
MACCLMS2
t
CLMMACS1
t
MACCLMS1
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CY39100Z484-125BBI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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