參數(shù)資料
型號(hào): CY39100V388-181MGC
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁(yè)數(shù): 23/86頁(yè)
文件大?。?/td> 1212K
代理商: CY39100V388-181MGC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 23 of 86
Cluster Memory Timing Parameter Values
Over the Operating Range
Channel Memory Timing Parameter Values
Over the Operating Range
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
–0.02
–0.22
0.94
0.79
0.77
0.44
0.4
0.2
0.9
0.8
0.5
0.6
0
0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.9
0.9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.6
0.6
0.3
0.3
0.3
0.3
0.5
0.5
0.1
0
I/O Standard
Output Delay Adjustments
Input Delay Adjustments
t
IOIN
t
CKIN
Fast Slew Rate
t
EA
Slow Slew Rate
(additional delay to fast slew rate)
t
IODSLOW
t
EASLOW
t
IOD
t
ER
t
ERSLOW
t
IOREGPIN
Parameter
Asynchronous Mode Parameters
t
CLMAA
t
CLMPWE
t
CLMSA
t
CLMHA
t
CLMSD
t
CLMHD
Synchronous Mode Parameters
t
CLMCYC1
t
CLMCYC2
t
CLMS
t
CLMH
t
CLMDV1
t
CLMDV2
t
CLMMACS1
t
CLMMACS2
t
MACCLMS1
t
MACCLMS2
Internal Parameters
t
CLMCLAA
233
200
181
125
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
10.2
11
12
17
20
ns
ns
ns
ns
ns
ns
5.5
1.8
0.9
5.5
0.4
6
6.5
2.2
1.1
6.5
0.6
10
3.2
1.8
10
0.9
12
4.0
2.0
12
1.0
2.0
1.0
6.0
0.5
9.5
5.0
2.8
0
10
5.0
3.0
0
10.5
5.5
3.8
0
15
8.0
4.0
0
20
10.0
5.0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
7.0
11
7.5
12
8.0
17
10
20
15
7.7
4.5
3.6
6.0
8.0
5.0
4.0
6.5
8.5
5.5
4.4
7.0
12
8.0
6.6
10
15
10
8.0
12
6
6
6.5
10
12
ns
Parameter
Dual-Port Asynchronous Mode Parameters
t
CHMAA
t
CHMPWE
5.5
t
CHMSA
1.8
t
CHMHA
0.9
t
CHMSD
5.5
t
CHMHD
0.4
t
CHMBA
233
200
181
125
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
10
11
12
17
20
ns
ns
ns
ns
ns
ns
ns
6.0
2.0
1.0
6.0
0.5
6.5
2.2
1.1
6.5
0.6
10
3.2
1.8
10
0.9
12
4.0
2.0
12
1.0
8.5
9.0
10.0
14.0
16.0
相關(guān)PDF資料
PDF描述
CY39100V208-125NI WIRE STRIPPER, 0.25MMWIRE STRIPPER, 0.25MM; Stripping Capacity:0.25mm
CY39100V208-125NTC WIRE STRIPPER, 0.30MMWIRE STRIPPER, 0.30MM; Stripping Capacity:0.3mm
CY39100V208-125NTI WIRE STRIPPER, 0.40MMWIRE STRIPPER, 0.40MM; Stripping Capacity:0.4mm
CY39100V208-181BBC CUTTERS, SIDE EXTRA FULL FLUSH 120MMCUTTERS, SIDE EXTRA FULL FLUSH 120MM; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Extra Full Flush; Head type:Tapered/Relieved; Length,
CY39100V208-181BBI CUTTERS, SIDE FULL FLUSH 120MMCUTTERS, SIDE FULL FLUSH 120MM; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Full Flush; Head type:Tapered/Relieved; Length, jaw:9mm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V388-181NC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V388-233MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V388-233MGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V388-233NTC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V388B-125MGC 功能描述:IC CPLD 100K GATE 388-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP(24x24) 包裝:托盤