參數(shù)資料
型號(hào)： CY37064VP48-100BAI
英文描述： Electrically-Erasable Complex PLD
中文描述： 電可擦除復(fù)雜可編程邏輯器件
文件頁(yè)數(shù)： 5/66頁(yè)
文件大?。?/td> 2069K
代理商： CY37064VP48-100BAI
Ultra37000 CPLD Family
Ultra37000: December 13, 1996
Revision: March 15, 2001
5
Low-Power Option
Each logic block can operate in high-speed mode for critical
path performance, or in low-power mode for power conserva-
tion. The logic block mode is set by the user on a logic block
by logic block basis.
Product Term Allocator
Through the product term allocator, software automatically dis-
tributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator pro-
vides two important capabilities without affecting performance:
product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Ultra37000 devices, prod-
uct terms are steered on an individual basis. Any number be-
tween 0 and 16 product terms can be steered to any macrocell.
Note that 0 product terms is useful in cases where a particular
macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator al-
lows sharing across groups of four output macrocells in a vari-
able fashion. The software automatically takes advantage of
this capability—the user does not have to intervene.
Note that neither product term sharing nor product term steer-
ing have any effect on the speed of the product. All worst-case
steering and sharing configurations have been incorporated in
the timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells
can either be I/O Macrocells, which include an I/O Cell which
is associated with an I/O pin, or buried Macrocells, which do
not connect to an I/O. The combination of I/O Macrocells and
buried Macrocells varies from device to device.
Buried Macrocell
Figure 2
displays the architecture of buried macrocells. The
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or asynchronously re-
set at the logic block level with the separate set and reset prod-
uct terms. Each of these product terms features programma-
ble polarity. This allows the registers to be set or reset based
on an AND expression or an OR expression.
Clocking of the register is very flexible. Four global synchro-
nous clocks and a product term clock are available to clock the
register. Furthermore, each clock features programmable po-
larity so that registers can be triggered on falling as well as
rising edges (see the Clocking section). Clock polarity is cho-
sen at the logic block level.
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input reg-
ister (D-type or latch) whose input comes from the I/O pin as-
sociated with the neighboring macrocell. The output of all bur-
ied macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2
illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried mac-
rocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage of
allowing significant logic reduction to occur in many applica-
tions.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-in-
terface applications. Bus-hold additionally allows unused de-
vice pins to remain unconnected on the board, which is partic-
ularly useful during prototyping as designers can route new
signals to the device without cutting trace connections to V
CC
or GND. For more information, see the application note “Un-
derstanding Bus-Hold
A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
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